The Intel® Advanced Vector Extensions (Intel® AVX) intrinsics are assembly-coded functions that call on Intel® AVX instructions, which are new vector SIMD instruction extensions for the IA-32 and Intel® 64 architectures. The Intel® Advanced Vector Extensions are architecturally similar to the Intel® Streaming SIMD Extensions (Intel® SSE) and double-precision floating-point portions of Intel® SSE2.
The prototypes for the Intel® AVX intrinsics are available in the immintrin.h file.
The Intel®
AVX intrinsics are supported on the IA-32 and Intel® 64 architectures built from 32nm process technology. They map directly to the Intel® AVX new instructions and other enhanced 128-bit SIMD instructions.
The Intel® Advanced Vector Extensions (Intel®
AVX) introduces 256-bit vector processing capability and includes two components on the Intel processor generations built from 32nm process and beyond:
- The first generation Intel®
AVX provides 256-bit SIMD register support, 256-bit vector floating-point instructions, enhancements to 128-bit SIMD instructions, and
support for three and four operand syntax.
- The Fused Multiply-Add (FMA) is another extension of Intel®
AVX that provides floating-point, fused multiply-add instructions supporting 256-bit and 128-bit SIMD vectors.
Functional Overview
Intel®
AVX and FMA provide comprehensive functional improvements over previous generations of SIMD instruction extensions. The functional improvements include:
- 256-bit floating-point arithmetic primitives: Intel®
AVX
enhances existing 128-bit floating-point arithmetic instructions with 256-bit capabilities for floating-point processing. FMA provides additional set of 256-bit floating-point processing capabilities with a rich set of fused-multiply-add and fused multiply-subtract primitives.
- Enhancements for flexible SIMD data movements: Intel®
AVX
provides a number of new data movement primitives to enable efficient SIMD programming in relation to loading non-unit-strided data into SIMD registers, intra-register SIMD data manipulation, conditional expression and branch handling, etc. Enhancements for SIMD data movement primitives cover 256-bit and 128-bit vector floating-point data, and across 128-bit integer SIMD data processing using VEX-encoded instructions.