The following table lists available compiler directives.
Some directives may perform differently on Intel® microprocessors than on non-Intel microprocessors.
Each general directive name is preceded by the prefix cDEC$; for example, cDEC$ ALIAS. Each OpenMP* Fortran directive name is preceded by the prefix c$OMP; for example, c$OMP ATOMIC. The c in either can be a c, C, *, or ! in fixed-form source code; only ! in free-form source code.
Name |
Description |
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Specifies an alternate external name to be used when referring to external subprograms. |
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Specifies that an entity in memory is aligned. |
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Applies attributes to variables and procedures. |
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Generates warning messages for undeclared variables. |
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Creates a variable whose existence can be tested during conditional compilation. |
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Specifies distribution for a DO loop. |
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Marks the beginning of an alternative conditional-compilation block to an IF directive construct. |
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Marks the beginning of an alternative conditional-compilation block to an IF directive construct. |
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Marks the end of a conditional-compilation block. |
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Sets fixed-form line length. This directive has no effect on freeform code. |
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Specifies that a routine should be inlined whenever the compiler can do so. |
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Uses freeform format for source code. |
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Specifies an identifier for an object module. |
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Marks the beginning of a conditional-compilation block. |
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Marks the beginning of a conditional-compilation block. |
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Specifies that the routines can be inlined. |
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Selects default integer size. |
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Assists the compiler's dependence analysis of iterative DO loops. |
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Specifies the loop count for a DO loop; this assists the optimizer. |
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Sends a character string to the standard output device. |
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(Default) Turns off warning messages for undeclared variables. |
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(Default) Uses standard FORTRAN 77 code formatting column rules. |
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Specifies that a routine should not be inlined. |
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Disables auto-parallelization for an immediately following DO loop. |
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Disables optimizations. |
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Disables a data prefetch from memory. |
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(Default) Disables a previous STRICT directive. |
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Disables the unrolling of a DO loop. |
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Disables loop unrolling and jamming. |
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Disables vectorization of a DO loop. |
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Specifies a library search path in an object file. |
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Enables optimizations. |
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Controls whether fields in records and data items in common blocks are naturally aligned or packed on arbitrary byte boundaries. |
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Specifies the memory starting addresses of derived-type items. |
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Enables auto-parallelization for an immediately following DO loop. |
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Enables a data prefetch from memory. |
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Modifies certain characteristics of a common block. |
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Selects default real size. |
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Controls SIMD vectorization of loops. |
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Disables Intel® Fortran features not in the language standard specified on the command line. |
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Removes a symbolic variable name created with the DEFINE directive. |
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Tells the compiler's optimizer how many times to unroll a DO loop. |
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Enables loop unrolling and jamming. |
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Specifies that all data is aligned in a DO loop. |
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Enables vectorization of a DO loop. |
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Directs the compiler to use non-temporal (that is, streaming) stores. |
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Disables vectorization of a DO loop. |
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Directs the compiler to use temporal (that is, non-streaming) stores. |
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Specifies that no data is aligned in a DO loop. |
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To use the following directives, you must specify compiler option -openmp (Linux and Mac OS X) or /Qopenmp (Windows).
For more information on compiler option -openmp (Linux* and Mac OS* X) and /Qopenmp (Windows*), refer to the option description in the Compiler Options reference.
Name |
Description |
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Specifies that a specific memory location is to be updated dynamically. |
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Synchronizes all the threads in a team. |
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Restricts access for a block of code to only one thread at a time. |
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Specifies that the iterations of the immediately following DO loop must be executed in parallel. |
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Specifies synchronization points where the implementation must have a consistent view of memory. |
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Specifies a block of code to be executed by the master thread of the team. |
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Specifies a block of code to be executed sequentially. |
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Defines a parallel region. |
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Defines a parallel region that contains a single DO directive. |
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Defines a parallel region that contains SECTIONS directives. |
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Defines a parallel region that contains a single WORKSHARE directive. |
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Specifies a block of code to be divided among threads in a team (a worksharing area). |
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Specifies a block of code to be executed by only one thread in a team. |
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Defines a task region. |
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Specifies a wait on the completion of child tasks generated since the beginning of the current task. |
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Makes named common blocks private to a thread but global within the thread. |
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Divides the work of executing a block of statements or constructs into separate units. |
Optimization Notice |
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Intel® Compiler includes compiler options that optimize for instruction sets that are available in both Intel® and non-Intel microprocessors (for example SIMD instruction sets), but do not optimize equally for non-Intel microprocessors. In addition, certain compiler options for Intel® Compiler are reserved for Intel microprocessors. For a detailed description of these compiler options, including the instruction sets they implicate, please refer to "Intel® Compiler User and Reference Guides > Compiler Options". Many library routines that are part of Intel® Compiler are more highly optimized for Intel microprocessors than for other microprocessors. While the compilers and libraries in Intel® Compiler offer optimizations for both Intel and Intel-compatible microprocessors, depending on the options you select, your code and other factors, you likely will get extra performance on Intel microprocessors. While the paragraph above describes the basic optimization approach for Intel® Compiler, with respect to Intel's compilers and associated libraries as a whole, Intel® Compiler may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel® Streaming SIMD Extensions 2 (Intel® SSE2), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Intel recommends that you evaluate other compilers to determine which best meet your requirements. |
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